1. Field of the Invention
The present invention relates to a memory system and a memory accessing method thereof, and more particularly, to a memory system with a flexible serial interface and a memory accessing method thereof.
2. Description of the Related Art
Generally, a synchronous dynamic random access memory (SDRAM), a rambus DRAM (RDRAM), a static RAM (SRAM) and a fast cycle RAM (FCRAM) are widely used a memory system. Most of them have a bus type parallel interface and uses an independent clock signal. A memory controller creates and outputs an address signal and a control signal to read and write data from/to the memory in response to a memory access instruction from a central processing unit (CPU). Also, the memory controller reads data from the memory through a data line and transfers the read data to the CPU or writes data from the CPU to the memory. As a semiconductor technology has been highly developed, the integrity has abruptly increased. Therefore, a CPU and a memory controller were often manufactured as a single chip.
A high performance CPU requires a broad bandwidth memory bus and a large memory space for storing great quantity of data. However, a conventional parallel memory interface requires a number of memory pins to dispose at the memory controller in order to accommodate large quantity of memory. Also, the conventional parallel memory interface must create data, address and control signals to be synchronized with a high clock in order to satisfy the broad bandwidth memory interface. In order to stably access a memory in high-clocking, the number of memories connected to a bus must be reduced, while minimizing the signal interference and the influence of reflection which are generated at a bus type memory interface.
In order to embody the memory interface on a print circuit board (PCB), there were many limitations existed in arranging related elements and related signal wiring, the number of layers increases, and an expensive and high-quality substrate is required. Also, methods for confronting malfunctioning of a memory bus are limited. For example, if more than two data buses are malfunctioned, it cannot be recovered.
Due to such a reason, there is a demand for an enhanced memory accessing method that can support a high performance CPU, be connected to a large capacity of memory in high speed, reduce a cost of designing a print circuit board, minimize an error, and have a confronting capability against malfunctioning of a memory interface.